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NXP Semiconductors /MIMXRT1062 /SystemControl /CSSELR

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Interpret as CSSELR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IND_0)IND 0 (LEVEL_0)LEVEL

LEVEL=LEVEL_0, IND=IND_0

Description

Cache Size Selection Register

Fields

IND

Instruction not data bit

0 (IND_0): Data or unified cache.

1 (IND_1): Instruction cache.
LEVEL

Cache level of required cache

0 (LEVEL_0): Level 1 cache.

1 (LEVEL_1): Level 2 cache.

2 (LEVEL_2): Level 3 cache.

3 (LEVEL_3): Level 4 cache.

4 (LEVEL_4): Level 5 cache.

5 (LEVEL_5): Level 6 cache.

6 (LEVEL_6): Level 7 cache.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data